Conventionally, various techniques have been known for obtaining an output signal with its phase being adjusted. For example, a Delay Locked Loop (DLL) is one of such techniques for obtaining an output signal with its phase being adjusted. In the DLL, for example, a delay unit that adds a delay amount to a phase is used. In the DLL, the delay unit adds the delay amount to the phase of an input signal, and a delay signal delayed in phase in comparison with the phase of the input signal is taken as an output signal. Japanese Laid-open Patent Publication Nos. 2007-293911, H11-7768, and 2004-15689 each disclose a scheme of correcting a phase shift between an input signal and a clock signal.
Meanwhile, the conventional technologies mentioned above have a problem in which the phase of the output signal cannot be finely adjusted.
For example, in the conventional technologies, each delay unit adds to the phase of the input signal a delay amount equal to or greater than a predetermined minimum value and equal to or smaller than a predetermined maximum value. Here, the predetermined minimum value is a propagation delay time of the delay unit itself, representing a phase resolution among delay units. Therefore, in the conventional technologies, the delay amount to be added to the phase of the input signal cannot be equal to or smaller than the predetermined minimum value, thereby making it impossible to finely adjust the phase of the output signal so that the phase is equal to or smaller than the predetermined minimum value. The three patent documents mentioned above do not disclose a technique of finely adjusting the phase of the output signal.